The invention relates to electronic circuitry comprising a plurality of successive stages, alternately odd and even stages, each stage comprising at least one combinatory logic circuit having at least one output connected to the input of an associated first latch, a clock signal being applied to a clock input of each first latch, the clock signal successively taking, during a clock cycle, a high level between a rising front and a descending front, and a low level from said descending front until the rising front of the next clock cycle, each first latch being transparent during the high level of the corresponding clock signal.
It also relates to a method for simulating disturbances.